HAL - INRIA :: [ensl-00640063, version 1] An FPGA architecture for solving the Table Maker's Dilemma

ensl-00640063, version 1

An FPGA architecture for solving the Table Maker's Dilemma

Florent de Dinechin ()^a^, 1, 2, Jean-Michel Muller () ¹, Bogdan Pasca () ¹, Alexandru Plesco () ³

Application-Specific Systems, Architectures and Processors (ASAP), 2011 IEEE International Conference on (2011) 187-194

Résumé : Solving the Table Maker's Dilemma, for a given function and a given target floating-point format, requires testing the value of the function, with high precision, at a very large number of consecutive values. We give an algorithm that allows for performing such computations on a very regular architecture, and present an FPGA implementation of that algorithm.

a – Ecole Normale Supérieure de Lyon - ENS Lyon
1 : ARENAIRE (Inria Grenoble Rhône-Alpes / LIP Laboratoire de l'Informatique du Parallélisme)
INRIA – CNRS : UMR5668 – Université Claude Bernard - Lyon I – École Normale Supérieure - Lyon
2 : Laboratoire de l'Informatique du Parallélisme (LIP)
Université de Lyon – CNRS : UMR5668 – INRIA – École Normale Supérieure - Lyon – Université Claude Bernard - Lyon I
3 : COMPSYS (INRIA Grenoble Rhône-Alpes / LIP Laboratoire de l'Informatique du Parallélisme)
INRIA – CNRS : UMR5668 – École Normale Supérieure - Lyon

ensl-00640063, version 1
http://hal-ens-lyon.archives-ouvertes.fr/ensl-00640063
oai:hal-ens-lyon.archives-ouvertes.fr:ensl-00640063
Contributeur : Jean-Michel Muller <>
Soumis le : Lundi 14 Novembre 2011, 13:49:41
Dernière modification le : Lundi 14 Novembre 2011, 14:01:20

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DOI : 10.1109/ASAP.2011.6043267

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