hal-00649635, version 1
Performance modeling for power consumption reduction on SCC
Bertrand Putigny
1, 2Brice Goglin
1, 2Denis Barthou
1, 2
4th Many-core Applications Research Community (MARC) Symposium (2011)
Résumé : As power is becoming one of the biggest challenge in high performance computing, we are proposing a performance model on the Single-chip Cloud Computer in order to predict both power consumption and runtime of regular codes. This model takes into account the frequency at which the cores of the SCC chip operate. Thus, we can predict the execution time and power needed to run the code for each available frequency. This allows to choose the best frequency to optimize several metrics such as power efficiency or minimizing power consumption, based on the needs of the application. Our model only needs some parameters that are code dependent. These parameters can be found through static code analysis. We validated our model by showing that it can predict performance and find the optimal frequency divisor to optimize energy efficiency on several dense linear algebra codes.
- 1 : Laboratoire Bordelais de Recherche en Informatique (LaBRI)
- CNRS : UMR5800 – Université Sciences et Technologies - Bordeaux I – École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB) – Université Victor Segalen - Bordeaux II
- 2 : RUNTIME (INRIA Bordeaux - Sud-Ouest)
- INRIA – CNRS : UMR5800 – Université Sciences et Technologies - Bordeaux I – École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)
- Domaine : Informatique/Architecture
- hal-00649635, version 1
- http://hal.inria.fr/hal-00649635
- oai:hal.inria.fr:hal-00649635
- Contributeur : Bertrand Putigny
- Soumis le : Jeudi 8 Décembre 2011, 12:35:57
- Dernière modification le : Jeudi 8 Décembre 2011, 12:35:57






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