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Communication Dans Un Congrès Année : 2012

An Efficient Power Estimation Methodology for Complex RISC Processor-based Platforms

Résumé

In this contribution, we propose an efficient power estima- tion methodology for complex RISC processor-based plat- forms. In this methodology, the Functional Level Power Analysis (FLPA) is used to set up generic power models for the different parts of the system. Then, a simulation framework based on virtual platform is developed to evalu- ate accurately the activities used in the related power mod- els. The combination of the two parts above leads to a het- erogeneous power estimation that gives a better trade-off be- tween accuracy and speed. The usefulness and effectiveness of our proposed methodology is validated through ARM9 and ARM CortexA8 processor designed respectively around the OMAP5912 and OMAP3530 boards. This efficiency and the accuracy of our proposed methodology is evaluated by using a variety of basic programs to complete media bench- marks. Estimated power values are compared to real board measurements for the both ARM940T and ARM CortexA8 architectures. Our obtained power estimation results pro- vide less than 3% of error for ARM940T processor, 3.5% for ARM CortexA8 processor-based system and 1x faster compared to the state-of-the-art power estimation tools.
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Dates et versions

hal-00675469 , version 1 (01-03-2012)

Identifiants

  • HAL Id : hal-00675469 , version 1

Citer

Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser, Smail Niar, Eric Senn. An Efficient Power Estimation Methodology for Complex RISC Processor-based Platforms. GLSVLSI 2012, GLSVLSI, May 2012, Salt lake city, UTAH, United States. ⟨hal-00675469⟩
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