Beyond CPU Frequency Scaling for a Fine-grained Energy Control of HPC Systems

Ghislain Landry Tsafack Chetsa; Laurent Lefevre; Jean-Marc Pierson; Patricia Stolf; Georges Da Costa

hal-00752883, version 1

Beyond CPU Frequency Scaling for a Fine-grained Energy Control of HPC Systems

Ghislain Landry Tsafack Chetsa () ^1, 2, Laurent Lefevre (, )^a^, 1, 3, Jean-Marc Pierson (, ) ⁴, Patricia Stolf () ⁴, Georges Da Costa (, ) ⁴

24th International Symposium on Computer Architecture and High Performance Computing (2012)

Résumé : Modern high performance computing subsystems (HPC) - including processor, network, memory, and IO - are provided with power management mechanisms. These include dynamic speed scaling and dynamic resource sleeping. Understanding the behavioral patterns of high performance computing systems at runtime can lead to a multitude of optimization opportunities including controlling and limiting their energy usage. In this paper, we present a general purpose methodology for optimizing energy performance of HPC systems consid- ering processor, disk and network. We rely on the concept of execution vector along with a partial phase recognition technique for on-the-fly dynamic management without any a priori knowledge of the workload. We demonstrate the effectiveness of our management policy under two real-life workloads. Experimental results show that our management policy in comparison with baseline unmanaged execution saves up to 24% of energy with less than 4% performance overhead for our real-life workloads.

a – INRIA
1 : École normale supérieure de Lyon (ENS LYON)
École Normale Supérieure - Lyon
2 : AVALON (LIP Lyon / Inria Grenoble Rhône-Alpes)
CNRS : UMR5668 – INRIA – École Normale Supérieure - Lyon – Laboratoire d'informatique du Parallélisme – Université Claude Bernard - Lyon I
3 : RESO (INRIA Grenoble Rhône-Alpes / LIP Laboratoire de l'Informatique du Parallélisme)
CNRS : UMR5668 – Université Claude Bernard - Lyon I – École Normale Supérieure - Lyon – Laboratoire de l'Informatique du Parallélisme – INRIA
4 : Institut de recherche en informatique de Toulouse (IRIT)
CNRS : UMR5505 – Institut National Polytechnique de Toulouse - INPT – Université des Sciences Sociales - Toulouse I – Université Toulouse I [UT1] Capitole – Université Toulouse le Mirail - Toulouse II – Université Paul Sabatier [UPS] - Toulouse III

hal-00752883, version 1
http://hal.inria.fr/hal-00752883
oai:hal.inria.fr:hal-00752883
Contributeur : Ghislain Landry Tsafack Chetsa <>
Soumis le : Vendredi 16 Novembre 2012, 15:43:08
Dernière modification le : Mercredi 30 Janvier 2013, 19:03:31

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%% hal-00752883, version 1
%% http://hal.inria.fr/hal-00752883
@inproceedings{tsafackchetsa:hal-00752883,
    hal_id = {hal-00752883},
    url = {http://hal.inria.fr/hal-00752883},
    title = {{Beyond CPU Frequency Scaling for a Fine-grained Energy Control of HPC Systems}},
    author = {Tsafack Chetsa, Ghislain Landry and Lefevre, Laurent and Pierson, Jean-Marc and Stolf, Patricia and Da Costa, Georges},
    abstract = {{Modern high performance computing subsystems (HPC) - including processor, network, memory, and IO - are provided with power management mechanisms. These include dynamic speed scaling and dynamic resource sleeping. Understanding the behavioral patterns of high performance computing systems at runtime can lead to a multitude of optimization opportunities including controlling and limiting their energy usage. In this paper, we present a general purpose methodology for optimizing energy performance of HPC systems consid- ering processor, disk and network. We rely on the concept of execution vector along with a partial phase recognition technique for on-the-fly dynamic management without any a priori knowledge of the workload. We demonstrate the effectiveness of our management policy under two real-life workloads. Experimental results show that our management policy in comparison with baseline unmanaged execution saves up to 24\% of energy with less than 4\% performance overhead for our real-life workloads.}},
    language = {Anglais},
    affiliation = {{\'E}cole normale sup{\'e}rieure de Lyon - ENS LYON , AVALON - LIP Lyon / Inria Grenoble Rh{\^o}ne-Alpes , RESO - INRIA Grenoble Rh{\^o}ne-Alpes / LIP Laboratoire de l'Informatique du Parall{\'e}lisme , Institut de recherche en informatique de Toulouse - IRIT},
    booktitle = {{24th International Symposium on Computer Architecture and High Performance Computing}},
    address = {New York City, {\'E}tats-Unis},
    audience = {internationale },
    year = {2012},
    month = Oct,
    pdf = {http://hal.inria.fr/hal-00752883/PDF/sbac-pad-fv.pdf},
}

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