inria-00108072, version 1
A compact Multi-Chip-Module Implementation of a Multi-Precision Neural Network Classifier
Amine Bermak aDominique Martinez b, 1
IEEE International Symposium on Circuits and Systems - ISCAS'2001 3 (2001) 249-252
Résumé : This paper describes a novel Multi-Chip Module (MCM) digital implementation of a reconfigurable multi-precision neural network classifier. The design is based on a scalable systolic architecture with a user defined topology and arithmetic precision of the neural network. Indeed, the MCM integrates 64/32/16 neurons with a corresponding accuracy of 4/8/16-bits. A prototype has been designed and successfully tested in CMOS 0.7 $\mu$m technology.
- a – EDITH COWAN UNIVERSITY
- b – CNRS
- 1 : CORTEX (INRIA Lorraine - LORIA)
- INRIA – CNRS : UMR7503 – Université Henri Poincaré - Nancy I – Université Nancy II – Institut National Polytechnique de Lorraine (INPL)
- Domaine : Informatique/Autre
- Mots-clés : neural networks – vlsi || réseaux de neurones – vlsi
- Référence interne : A01-R-044 || bermak01a
- Commentaire : Colloque avec actes et comité de lecture. internationale.
- inria-00108072, version 1
- http://hal.inria.fr/inria-00108072
- oai:hal.inria.fr:inria-00108072
- Contributeur : Publications Loria
- Soumis le : Jeudi 19 Octobre 2006, 15:40:46
- Dernière modification le : Mardi 24 Octobre 2006, 12:08:59
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