Many cryptosystems embed a high-quality true random number generator (TRNG). The randomness quality of a TRNG output stream depends on its implementation and may vary due to various changes in the environment such as power supply, temperature, electromagnetic interferences. Attacking TRNGs may be a good solution to decrease the security of a cryptosystem leading to lower security keys or bad padding values for instance. In order to protect TRNGs, on-the-fly evaluation of their randomness quality must be integrated on the chip. In this paper, we present some preliminary results of the FPGA implementation of functional units dedicated to statistical tests for on-the-fly randomness evaluation. In the entropy test the evaluation of the harmonic series at some ranks is required. Usually its approximation is costly. We propose a multiple interval polynomial approximation. The decomposition of the whole domain into small sub-intervals leads to a good trade-off between the degree of the polynomial (i.e. multipliers cost) and the memory resources required to store the coefficients for all sub-intervals.