inria-00438594, version 1
A Flow Scheduler Architecture
Dinil Mon Divakaran
a, 1Giovanna Carofiglio
b, 2Eitan Altman
3Pascale Primet
a, 1
N° RR-7133 (2009)
Abstract: Scheduling flows in the Internet has sprouted much interest in the research community leading to the development of many queueing models, capitalizing on the heavy-tail property of flow size distribution. Theoretical studies have shown that ‘size-based' schedulers improve the delay of small flows without almost no performance degradation to large flows. On the practical side, the issues in taking such schedulers to implementation have hardly been studied. This work looks into practical aspects of making size-based scheduling feasible in future Internet. In this context, we propose a flow scheduler architecture comprising three modules — Size-based scheduling, Threshold-based sampling and Knockout buffer policy — for improving the performance of flows in the Internet. Unlike earlier works, we analyze the performance using five different performance metrics, and through extensive simulations show the goodness of this architecture.
- a – INRIA
- b – Alcatel-Lucent Bell Labs
- 1: RESO (INRIA Grenoble Rhône-Alpes / LIP Laboratoire de l'Informatique du Parallélisme)
- CNRS : UMR5668 – Université Claude Bernard - Lyon I – École Normale Supérieure - Lyon – Laboratoire de l'Informatique du Parallélisme – INRIA
- 2: Alcatel Lucent Bell Labs
- ALCATEL
- 3: MAESTRO (INRIA Sophia Antipolis)
- INRIA – Université Montpellier II - Sciences et Techniques du Languedoc
- Domain : Computer Science/Networking and Telecommunication
- Keywords : Scheduling – Sampling – QoS – Future Internet – Architecture
- Internal note : RR-7133
- inria-00438594, version 1
- http://hal.inria.fr/inria-00438594
- oai:hal.inria.fr:inria-00438594
- From: Dinil Mon Divakaran
- Submitted on: Monday, 7 December 2009 11:02:59
- Updated on: Monday, 7 December 2009 16:45:45






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