Multi-domain processors characterized by multiple clock/voltage and power domains are widely used to manage power in modern nano-scale processor designs, especially in large scale multi- or many-core systems that require aggressive power management methodologies. One such example is the 48-core prototype processor recently announced by Intel Corp. In order to understand the challenges and opportunities in this problem space, this tutorial presents a comprehensive overview of advanced design techniques in multi-domain clock and power management for high-performance processors, as well as low power systems-on-chip (SoCs). As the number of components on a single chip and their performance continue to increase, the design of the communication architecture plays a major role. From this perspective, this tutorial addresses the network-on-chip (NoC) design and presents several research issues where the concept of “network” is at the forefront of multi/many-core processing. NoCs are suitable for large high-performance chip multiprocessors as well as SoCs, all of which increasingly employing a multi- domain design style. Consequently, the tutorial surveys asynchronous routers for various architectures and asynchronous interconnections that enable higher bandwidth and lower power. The tutorial will discuss these issues and outline existing approaches to overcome any inherent deficiencies and fully enable the aforementioned technology. In addition to the on-chip communication problem, the twin concern of increased power consumption of future multi/many-core systems needs to be addressed, especially in the presence of workload and parameter variations. For multi-core designs, the concept of multiple voltage/frequency islands (VFIs) is typically used to enable fine-grain power management. In such a system, each island can work at its own speed, while the communication across different VFIs is achieved through mixed clock/mixed voltage FIFOs. We plan to discuss the design and management of novel NoC architectures partitioned into multiple VFIs, as well as online feedback control mechanisms that can dynamically adjust the operating voltage and frequency around some statically prescribed values. Finally, considering variability effects at micro-architecture and architecture levels is needed for determining variation-aware dynamic power management algorithms that are most likely to meet performance and power constraints. Towards this end, we plan to discuss modeling the effects of process variation at micro-architecture/architecture level in modern multi/many-core, multi-domain systems and show how dynamic power management mechanisms can be developed such that these systems behave in a robust manner in the presence of process technology parameter variation. Of extreme importance is the ability to provide workload- and process variability-driven adaptability not only through a static assignment of local voltages/frequencies, but also using dynamic application mapping and on-the-fly voltage/frequency scaling.