inria-00614597, version 3
Damaris: Leveraging Multicore Parallelism to Mask I/O Jitter
Matthieu Dorier
a, 1Gabriel Antoniu
b, 2Franck Cappello
3, 4, 5Marc Snir c, 6Leigh Orf
d, 7
N° RR-7706 (2012)
Résumé : With exascale computing on the horizon, the performance variability of I/O systems represents a key challenge in sustaining high performance. In many HPC applications, I/O is concurrently performed by all processes, which leads to I/O bursts. This causes resource contention and substantial variability of I/O performance, which significantly impacts the overall application performance together with the predictability of its run time. In this paper, we first illustrate the presence of I/O jitter on different platforms, and show the impact of different user-configurable parameters and I/O approaches on write performance variability. We then propose a new approach to I/O, called Damaris, which leverages dedicated I/O cores on each multicore SMP node, along with the use of shared-memory, to efficiently perform asynchronous data processing and I/O. We evaluate our approach on three different platforms including the Kraken Cray XT5 supercomputer, with the CM1 atmospheric model, which is one of the target HPC applications for the Blue Waters project. By overlapping I/O with computation and by gathering data into large files while avoiding synchronization between cores, our solution brings several benefits: 1) it fully hides the jitter as well as all I/O-related costs, which makes simulation performance predictable; 2) it increases the sustained write throughput by a factor of 15 compared to standard approaches; 3) it allows almost perfect scalability of the simulation where other I/O approaches fail to scale; 4) it enables a 600% compression ratio without any additional overhead, leading to a major reduction of storage requirements.
- a – ENS Cachan Brittany
- b – INRIA
- c – University Of Illinois at Urbana Champaign
- d – Central Michigan University
- 1 : École normale supérieure de Cachan, antenne de Bretagne (ENS Cachan Bretagne)
- École normale supérieure de Cachan - ENS Cachan
- 2 : KerData (INRIA - IRISA)
- INRIA – CNRS : UMR6074 – École normale supérieure de Cachan - ENS Cachan – Institut National des Sciences Appliquées (INSA) - Rennes – Université de Rennes 1
- 3 : GRAND-LARGE (INRIA Saclay - Ile de France)
- INRIA – CNRS : UMR8623 – Université Paris XI - Paris Sud
- 4 : Joint Laboratory for Petascale Computing [Illinois] (JLPC)
- University of Illinois at Urbana-Champaign – INRIA
- 5 : Laboratoire de Recherche en Informatique (LRI)
- CNRS : UMR8623 – Université Paris XI - Paris Sud
- 6 : Department of Computer Science [UIUC] (UIUC)
- University of Illinois at Urbana-Champaign
- 7 : University of Michigan
- University of Michigan
- Collaboration : Joint INRIA/UIUC Laboratory for Petascale Computing, Grid'5000
- Domaine : Informatique/Calcul parallèle, distribué et partagé
- Mots-clés : Exascale Computing – Multicore Architectures – I/O – Variability – Dedicated Cores
- Référence interne : RR-7706
- Versions disponibles : v1 (12-08-2011) v2 (07-12-2011) v3 (09-04-2012)
- inria-00614597, version 3
- http://hal.inria.fr/inria-00614597
- oai:hal.inria.fr:inria-00614597
- Contributeur : Matthieu Dorier
- Soumis le : Lundi 9 Avril 2012, 14:29:07
- Dernière modification le : Jeudi 6 Septembre 2012, 11:56:12






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