Latch optimization in circuits generated from high-level descriptions

Ellen M. Sentovich; Horia Toma; Gérard Berry

hal-00618122, version 1

Latch optimization in circuits generated from high-level descriptions

Ellen M. Sentovich ¹, Horia Toma ², Gérard Berry ²

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design (1996) Pages 428-435 - ISBN: 0-8186-7597-7

Abstract: In a gate-level description of a finite state machine (FSM), there is a tradeoff between the number of latches and the size of the logic implementing the next-state and output functions. Typically, an initial implementation is generated via explicit state assignment or translation from a high-level language, and the tradeoff is subsequently only lightly explored. We efficiently explore good latch/logic tradeoffs for large designs generated from high-level specifications. We reduce the number of latches while controlling the logic size. We demonstrate the efficacy of our techniques on some large industrial examples.

1: MEIJE (INRIA Sophia Antipolis)
INRIA
2: Centre de Mathématiques Appliquées (CMA)
MINES ParisTech - École nationale supérieure des mines de Paris

hal-00618122, version 1
http://hal-ensmp.archives-ouvertes.fr/hal-00618122
oai:hal-ensmp.archives-ouvertes.fr:hal-00618122
From: Brigitte Hanot <>
Submitted on: Wednesday, 31 August 2011 17:06:50
Updated on: Wednesday, 31 August 2011 17:06:50

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DOI: 10.1109/ICCAD.1996.569833

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