Abstract: The delay of instructions broadcast has a significant impact on the performance of Single Instruction Multiple Data (SIMD) architecture. This is especially true for massively parallel processing Systems-on-Chip (mppSoC), where the processing stage and that of setting up the communication mechanism need several clock periods. The subnetting is a technique to adapt the plan address of a network according to the number of nodes it should contain. The choice of this model is efficient to better control the broadcast instructions domain and the data traffic between network nodes while maintaining the aspect of synchronous communication separate from asynchronous processing. In this paper, we describe the design of broadcast with mask mapping dedicated to mppSoC architecture to reduce performance degradation when the number of processors increases. Then, we validate this proposed approach and we show its effectiveness by the simulation results and the FPGA implementation.