33872 articles – 26722 Notices  [english version]
.:. Consultation > Par auteur > Auvergne .:.
2 documents classés par :

A Performance Driven Layout Synthesis Approach for Digital CMOS Cell Implementation
Robert M., Cathebras G., Azemard N., Deschacht D., Auvergne D.
VLSI integration N/A (1993) N/A [lirmm-00239254 - version 1]
Evaluation of VLSI Layout Implementation for Efficiency
Robert M., Trauchessec J., Cathebras G., Bonzom V., Azemard N., Deschacht D., Auvergne D.
Dans EURO-ASIC'91: The European Conference on Design Automation with The European Event in ASIC Design (1991) 362-365 [lirmm-00239384 - version 1]