34272 articles – 26874 Notices  [english version]
.:. Consultation > Par auteur > André .:.
38 documents classés par :
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fulltext access Modèles de temps et de contraintes temporelles de MARTE et leurs applications
André C.
N° RR-7788 (2011) [hal-00639211 - version 1]
Logical Time: observation vs. implementation
Mallet F., André C., De Simone R.
ACM SIGSOFT Software Engineering Notes 36, 1 (2011) 1--8 [inria-00576647 - version 1]
fulltext access Logical time @ work: the RT-Simex project
Deantoni J., Mallet F., André C., Thomas F.
Dans Sophia Antipolis Formal Approach (2011) [inria-00587151 - version 1]
The Time Model of Logical Clocks available in the OMG MARTE profile
André C., Deantoni J., Mallet F., De Simone R.
Dans Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, Springer Science+Business Media, LLC 2010 (Ed.) (2010) 28 [inria-00495664 - version 1]
Un processus automatique pour concevoir les profils UML
Mallet F., André C., Lagarde F.
Technique et Science Informatiques (TSI) 29, 5 (2010) 391-419 [inria-00482745 - version 1]
fulltext access Un profil UML pour la modélisation multiniveau
Mallet F., André C., Lagarde F.
N° RR-7287 (2010) [inria-00482727 - version 1]
VHDL Observers for Clock Constraint Checking
André C., Mallet F., Deantoni J.
Dans Symposium on Industrial Embedded Systems (2010) [inria-00587107 - version 1]
The Clock Constraint Specification Language for building timed causality models
Mallet F., Deantoni J., André C., De Simone R.
Innovations in Systems and Software Engineering 6, 1-2 (2010) 99-106 [inria-00464894 - version 1]
fulltext access An Automated Process for Implementing Multilevel Domain Models
Mallet F., Lagarde F., André C., Gérard S., Terrier F.
Dans Software Language Engineering (2009) 314-333 [inria-00464880 - version 1]
fulltext access Verification of clock constraints: CCSL Observers in Esterel
André C.
N° RR-7211 (2010) [inria-00458847 - version 1]