8715 articles  [version française]
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6 documents ordered by :

fulltext access Modular termination of C programs
Andrieu G., Alias C., Gonnord L.
N° RR-8166 (2012) [hal-00760917 - version 2]
fulltext access FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores
Alias C., Pasca B., Plesco A.
N° RR-7674 (2011) [inria-00606977 - version 1]
fulltext access Kernel Offloading with Optimized Remote Accesses
Alias C., Darte A., Plesco A.
N° RR-7697 (2011) [inria-00611179 - version 1]
fulltext access Program Analysis and Source-Level Communication Optimizations for High-Level Synthesis
Alias C., Darte A., Plesco A.
N° RR-7648 (2011) [inria-00601822 - version 1]
fulltext access Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators. An Experience with the Altera C2H HLS Tool.
Alias C., Darte A., Plesco A.
N° RR-7281 (2010) [inria-00482035 - version 1]
fulltext access Bounding the Computational Complexity of Flowchart Programs with Multi-dimensional Rankings
Alias C., Darte A., Feautrier P., Gonnord L.
N° RR-7235 (2010) [inria-00464356 - version 1]