inria-00596241, version 2
Logico-Numerical Abstract Acceleration and Application to the Verification of Data-Flow Programs
N° RR-7630 (2012)
Abstract: Acceleration methods are commonly used for speeding up the convergence of loops in reachability analysis of counter machine models. Applying these methods to synchronous data-flow programs with Boolean and numerical variables, e.g., Lustre programs, requires the enumeration of the Boolean states in order to obtain a control flow graph (CFG) with numerical variables only. Our goal is to apply acceleration techniques to data-flow programs without resorting to this exhaustive enumeration. To this end, we present (1) logico-numerical abstract acceleration methods for CFGs with Boolean and numerical variables and (2) partitioning techniques that make logical-numerical abstract acceleration effective. Experimental results show that incorporating these methods in a verification tool based on abstract interpretation provides not only significant advantage in terms of accuracy, but also a gain in performance in comparison to standard techniques.
- a – INRIA
- 1:
- INRIA – Institut polytechnique de Grenoble (Grenoble INP) – Université Joseph Fourier - Grenoble I – Université Pierre-Mendès-France - Grenoble II – CNRS : UMR5217
- Domain : Computer Science/Embedded Systems
- Keywords : Verification – Static Analysis – Abstract Interpretation – Abstract Acceleration – Control Flow Graph Partitioning
- Internal note : RR-7630
- Available versions : v1 (2011-05-27) v2 (2012-11-19)
- inria-00596241, version 2
- http://hal.inria.fr/inria-00596241
- oai:hal.inria.fr:inria-00596241
- From:
- Submitted on: Monday, 19 November 2012 11:56:34
- Updated on: Thursday, 22 November 2012 15:44:44





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