Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

Cyrille Chavet; Philippe Coussy; Eric Martin; Pascal Urard

hal-00455121, version 1

Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

Cyrille Chavet (, ) ^1, 2, Philippe Coussy () ¹, Eric Martin () ¹, Pascal Urard ²

35th International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2010 (2010) Pages: 1594-1597, Paper ID : 2559

Abstract: For high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low Density Parity Check (LDPC) and Turbo-Codes. In this paper we propose a methodology which finds a collision-free mapping of the variables in the memory banks and which optimizes the resulting interleaving architecture. Finally, we show through a pedagogical example the interest of our approach compared to state-of-the-art techniques.

1: Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC)
CNRS : UMR3192 – Université de Bretagne Occidentale [UBO] – Université de Bretagne Sud – Institut Mines-Télécom – Télécom Bretagne – PRES Université Européenne de Bretagne [UEB] – Institut Supérieur des Sciences et Technologies de Brest (ISSTB)
2: ST Microelectronics (ST MICROELECTRONICS)
STMicrelectronics

hal-00455121, version 1
http://hal.archives-ouvertes.fr/hal-00455121
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From: Cyrille Chavet <>
Submitted on: Tuesday, 9 February 2010 15:39:06
Updated on: Monday, 24 January 2011 11:23:37

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arXiv: 1002.3990

DOI: 10.1109/ICASSP.2010.5495535

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