inria-00424016, version 2
Fast architectures for the $\eta_T$ pairing over small-characteristic supersingular elliptic curves
IEEE Transactions on Computers 60, 2 (2011) 266-281
- a – University of Tsukuba
- b – INRIA
- c – Université Henri Poincaré - Nancy I
- d – Insituto Politécnico Nacional
- 1 :
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University of Tsukuba 1-1-1 Tennodai, Tsukuba, Ibaraki, 305-8573 Japon - 2 :
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INRIA – CNRS : UMR7503 – Université de Lorraine France - 3 :
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http://www.cinvestav.mx/
Centro de Investigacion y de Estudios Avanzados del IPN Avenida Politécnico Nacional 2508 Mexico-D.F. 07360 Mexique
Références bibliographiques
- Type de publication : Articles dans des revues avec comité de lecture
- Domaine :
Informatique/Cryptographie et sécurité Informatique/Arithmétique des ordinateurs Informatique/Architecture - Titre : Fast architectures for the $\eta_T$ pairing over small-characteristic supersingular elliptic curves
- Résumé : This paper is devoted to the design of fast parallel accelerators for the cryptographic $\eta_T$ pairing on supersingular elliptic curves over finite fields of characteristics two and three. We propose here a novel hardware implementation of Miller's algorithm based on a parallel pipelined Karatsuba multiplier. After a short description of the strategies we considered to design our multiplier, we point out the intrinsic parallelism of Miller's loop and outline the architecture of coprocessors for the $\eta_T$ pairing over $\F_{2^m}$ and $\F_{3^m}$. Thanks to a careful choice of algorithms for the tower field arithmetic associated with the $\eta_T$ pairing, we manage to keep the pipelined multiplier at the heart of each coprocessor busy. A final exponentiation is still required to obtain a unique value, which is desirable in most cryptographic protocols. We supplement our pairing accelerators with a coprocessor responsible for this task. An improved exponentiation algorithm allows us to save hardware resources. According to our place-and-route results on Xilinx FPGAs, our designs improve both the computation time and the area-time trade-off compared to previously published coprocessors.
- Langue du document : Anglais
- Titre de la revue :
IEEE Transactions on Computers Publisher Institute of Electrical and Electronics Engineers (IEEE) ISSN 0018-9340 - Date de publication : 01/02/2011
- Audience : internationale
- Editeur commercial : IEEE Computer Society
- Titre volume : Special Section on Computer Arithmetic
- Volume : 60
- Numéro : 2
- Pagination : 266-281
- DOI : 10.1109/TC.2010.163
Liste des fichiers attachés à ce document :
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bdeor_ieee_tc_arith.pdf |
- inria-00424016, version 2
- http://hal.inria.fr/inria-00424016
- oai:hal.inria.fr:inria-00424016
- Contributeur :
- Soumis le : Jeudi 25 Novembre 2010, 15:05:28
- Dernière modification le : Mercredi 9 Février 2011, 17:03:06




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