Integrating Hardware Limitations in CAN Schedulability Analysis

Dawood Khan; Reinder Bril; Nicolas Navet

inria-00542635, version 1

Integrating Hardware Limitations in CAN Schedulability Analysis

Dawood Khan ()^a^, 1, Reinder Bril ()^b^, 2, Nicolas Navet ()^a^, 1

8th International Workshop on Factory Communication Systems (2010)

Résumé : The existing schedulability analysis for the Controller Area Network (CAN) does not take into account that a CAN controller has finite buffer space to store outgoing messages and high priority messages may suffer from priority inversion if the buffers are already occupied by low priority messages. This gives rise to an additional delay for high priority messages, which, if not considered, may result in a deadline violation. In this paper, we explain the cause of this additional delay and extend the existing CAN schedulability analysis to integrate it. Finally,we suggest implementation guidelines that minimizes both the run-time CPU overhead and the additional delay due to priority inversion.

a – INRIA
b – Technische Universiteit Eindhoven
1 : TRIO (INRIA Lorraine - LORIA)
INRIA – CNRS : UMR7503 – Université Henri Poincaré - Nancy I – Université Nancy II – Institut National Polytechnique de Lorraine (INPL)
2 : Eindhoven University of Technology (TUE)
Eindhoven University of Technology

inria-00542635, version 1
http://hal.inria.fr/inria-00542635
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Contributeur : Dawood Khan <>
Soumis le : Vendredi 3 Décembre 2010, 09:46:46
Dernière modification le : Vendredi 3 Décembre 2010, 11:24:40

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