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Emerging Trends in Technological Innovation First IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2010, Costa de Caparica, Portugal, February 22-24, 2010 |
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Conference papers
Structural DfT Strategy for High-Speed ADCs
Abstract : This paper presents a Design-for-Test (DfT) approach
for folded ADCs. A sensor DfT circuit is designed to sample several
internal ADC test points at the same time, so that, by computing the
relative deviation among them the presence of defects can be detected. A
fault evaluation is done considering a behavioral model to compare the
coverage of the proposed test approach with a functional test.
Afterwards, a fault simulation is used on a transistor level
implementation of the ADC to establish the optimum threshold limits for
the DfT circuit that maximize the fault coverage figure.
Cited literature [12 references]
https://hal.inria.fr/hal-01060779
Contributor : Hal Ifip <>
Submitted on : Thursday, November 23, 2017 - 4:36:53 PM
Last modification on : Wednesday, November 29, 2017 - 12:08:50 PM
Contributor : Hal Ifip <>
Submitted on : Thursday, November 23, 2017 - 4:36:53 PM
Last modification on : Wednesday, November 29, 2017 - 12:08:50 PM
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