Emerging Trends in Technological Innovation First IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2010, Costa de Caparica, Portugal, February 22-24, 2010
Conference papers
Reconfigurable Circuits Using Magnetic
Tunneling Junction Memories
Abstract : This paper presents the first results of our work to
research and develop new reconfigurable circuits and topologies based on
Magnetic RAM (MRAM) memory elements. This work proposes a coarse-grained
reconfigurable array using MRAM. A coarse-grained array, where each
reconfigurable element computes on 4-bit or larger input words, is more
suitable to execute data-oriented algorithms and is more able to exploit
large amounts of operation-level parallelism than common fine-grained
architectures. The architecture is organized as a one-dimensional array
of programmable ALU and the configuration bits are stored in MRAM. MRAM
provide non-volatility with cell areas and with access speeds comparable
to those of SRAM and with lower process complexity than FLASH memory.
MRAM can also be efficiently organized as multi-context
memories.
https://hal.inria.fr/hal-01060781
Contributor : Hal Ifip <>
Submitted on : Friday, November 17, 2017 - 4:12:35 PM Last modification on : Saturday, June 1, 2019 - 11:26:02 AM Long-term archiving on: : Sunday, February 18, 2018 - 4:59:28 PM
Victor Silva, Jorge Fernandes, Horácio Neto. Reconfigurable Circuits Using Magnetic
Tunneling Junction Memories. First IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Feb 2010, Costa de Caparica, Portugal. pp.548-556, ⟨10.1007/978-3-642-11628-5_61⟩. ⟨hal-01060781⟩