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Generating VHDL source code from UML models of embedded systems

Abstract : Embedded systems' complexity and amount of distinct functionalities have increased over the last years. To cope with such issues, the projects' abstraction level is being continuously raised, and, in addition, new design techniques have also been used to shorten design time. In this context, Model-Driven Engineering approaches that use UML models are interesting options to design embedded systems, aiming at code generation of software and hardware components. Source code generation from UML is already supported by several commercial tools for software. However, there are only few tools addressing generation code using hardware description languages, such as VHDL. This work proposes an approach to generate automatically VHDL source code from UML specifications. This approach is supported by the GenERTiCA tool, which has been extended to support VHDL code generation. To validate this work, a use case focused in maintenance systems attended by embedded systems is presented.
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Contributor : Jean-François Pétin <>
Submitted on : Thursday, January 7, 2016 - 3:25:25 PM
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Tomas G. Moreira, Marco A. Wehrmeister, Carlos Eduardo Pereira, Jean-François Pétin, Eric Levrat. Generating VHDL source code from UML models of embedded systems. 7th IFIP TC 10 Working Conference on Distributed, Parallel and Biologically Inspired Systems (DIPES) / 3rd IFIP TC 10 International Conference on Biologically-Inspired Collaborative Computing (BICC) / Held as Part of World Computer Congress (WCC), Sep 2010, Brisbane, Australia. pp.125-136, ⟨10.1007/978-3-642-15234-4_13⟩. ⟨hal-00533288⟩



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