Skip to Main content Skip to Navigation
Conference papers

Some Hardware Aspects of the BESM-6 Design

Abstract : This paper very shortly describes some hardware solutions of central processor (CPU) of BESM-6. CPU had very deep instruction pipe with an associative buffer for instructions and an associative buffer for data with original protocol. Logical and storage elements used only domestic discrete components. Main logical unit based on differential amplifier with pyramid of rich diode logic and paraphase synchronization. Original construction without printed plate made wire connections very short and gave possibilities for direct access to every contacts and interchanging modules. All these solutions permitted to achieve high clock frequency, reliability and effective maintenance.
Complete list of metadatas

https://hal.inria.fr/hal-01568415
Contributor : Hal Ifip <>
Submitted on : Tuesday, July 25, 2017 - 11:43:09 AM
Last modification on : Tuesday, July 25, 2017 - 12:54:45 PM

File

978-3-642-22816-2_3_Chapter.pd...
Files produced by the author(s)

Licence


Distributed under a Creative Commons Attribution 4.0 International License

Identifiers

Citation

V. Smirnov. Some Hardware Aspects of the BESM-6 Design. 1st Soviet and Russian Computing (SoRuCom), Jul 2006, Petrozavodsk, Russia. pp.20-25, ⟨10.1007/978-3-642-22816-2_3⟩. ⟨hal-01568415⟩

Share

Metrics

Record views

83

Files downloads

156