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VLSI-SoC: Forward-Looking Trends in IC and Systems Design 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010 Madrid, Spain, September 27-29, 2010 |
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Conference papers
A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4
Abstract : This paper presents a low power 2.4-GHz fully integrated 1 MHz resolution IEEE 802.15.4 frequency synthesizer designed using 0.18um CMOS technology. An integer-N fully programmable divider employs a novel True-single-phase-clock (TSPC) 47/48 prescaler and a 6 bit P and S counters to provide the 1 MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillator (S-QVCO) to generate quadrature signals. The PLL consumes 3.6 mW of power at 1.8 V supply with the fully programmable divider consuming only 600 uW. The S-QVCO consumes 2.8 mW of power with a phase noise of -122dBc/Hz at 1 MHz offset.
Cited literature [17 references]
https://hal.inria.fr/hal-01516000
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Submitted on : Friday, April 28, 2017 - 2:29:51 PM
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Contributor : Hal Ifip Connect in order to contact the contributor
Submitted on : Friday, April 28, 2017 - 2:29:51 PM
Last modification on : Thursday, March 5, 2020 - 5:40:13 PM
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