Power Reduction in Embedded Systems Using a Design Methodology Based on Synchronous Finite State Machines

Abstract : To achieve the highest levels of power reduction, embedded systems must be conceived as low-power devices, since the early stages of the design process. The proposed Model-Based-Development process uses Synchronous Finite State Machines (SFSM) to model the behavior of low-power devices. This methodology is aimed at devices at the lower-end of the complexity spectrum, as long as the device behavior can be modeled as SFSM. The implementation requires a single timer to provide the SFSM clock. The energy reduction is obtained by changing the state of the processor to a low-power state, such as deep-sleep.The main contribution is the use of a methodology where energy consumption awareness is a concern from the early stages of the design cycle, and not an afterthought to the implementation phase.
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Douglas Renaux, Fabiana Pöttker. Power Reduction in Embedded Systems Using a Design Methodology Based on Synchronous Finite State Machines. 4th International Embedded Systems Symposium (IESS), Jun 2013, Paderborn, Germany. pp.61-72, ⟨10.1007/978-3-642-38853-8_6⟩. ⟨hal-01466694⟩

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