Table of Contents
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VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design
Andreas Burg, Ayse Coskun, Matthew Guthaus, Srinivas Katkoori, Ricardo Reis |
Front Matter |
FPGA-Based High-Speed Authenticated Encryption System
Michael Muehlberghuber, Christoph Keller, Frank Gürkaynak, Norbert Felber |
1-20 |
A Smart Memory Accelerated Computed Tomography Parallel Backprojection
Qiuling Zhu, Larry Pileggi, Franz Franchettis |
21-44 |
Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure
Andy Motten, Luc Claesen, Yun Pan |
45-63 |
Spatially-Varying Image Warping: Evaluations and VLSI Implementations
Pierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank Gürkaynak, Aljoscha Smolic |
64-87 |
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing
Jeremy Constantin, Ahmed Dogan, Oskar Andersson, Pascal Meinerzhagen, Joachim Rodrigues, David Atienza, Andreas Burg |
88-106 |
Configurable Low-Latency Interconnect for Multi-core Clusters
Giulia Beanato, Igor Loi, Giovanni Micheli, Yusuf Leblebici, Luca Benini |
107-124 |
A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks
Zhibin Xiao, Bevan Baas |
125-143 |
Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections
Anelise Kologeski, Caroline Concatto, Fernanda Kastensmidt, Luigi Carro |
144-161 |
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors
Davide Sabena, Luca Sterpone, Matteo Sonza Reorda |
162-180 |
SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture
Seokjoong Kim, Matthew Guthaus |
181-195 |
CMOS Implementation of Threshold Gates with Hysteresis
Farhad Parsan, Scott Smith |
196-216 |
Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates
Neil Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra, Paul Franzon |
217-233 |
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