index - VLSI-SoC: Design for Reliability, Security, and Low Power

Table of Contents
VLSI-SoC: Design for Reliability, Security, and Low Power *Youngsoo Shin, Chi-Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis (Eds.)*	Front Matter

On the Use of System-on-Chip Technology in Next-Generation Instruments Avionics for Space Exploration *Xabier Iturbe, Didier Keymeulen, Patrick Yiu, Daniel Berisford, Robert Carlson, Kevin Hand, Emre Ozer*	1 - 22
Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs *Raimund Ubar, Lembit Jürimägi, Elmet Orasson, Jaan Raik*	23-45
A Hardware Accelerator for Real Time Sliding Window Based Pedestrian Detection on High Resolution Images *Asim Khan, Muhammad Khan, Muhammad Bilal, Chong-Min Kyung*	46-66
Wearable ECG SoC for Wireless Body Area Networks: Implementation with Fuzzy Decision Making Chip *Manikandan Pandiyan, Geetha Mani*	67-86
Delay Testing Based on Multiple Faulty Behaviors *Masahiro Fujita*	87-108
A Temperature-Aware Battery Cycle Life Model for Different Battery Chemistries *Enrico Macii, Massimo Poncino, Alberto Bocca, Alessandro Sassone, Donghwa Shin, Alberto Macii*	109-130
A SAR Pipeline ADC Embedding Time Interleaved DAC Sharing for Ultra-low Power Camera Front Ends *Anvesha Amaravati, Manan Chugh, Arijit Raychowdhury*	131-149
Electromagnetic Transmission of Intellectual Property Data to Protect FPGA Designs *Lilian Bossuet, Pierre Bayon, Viktor Fischer*	150 - 169
JAIP-MP: A Four-Core Java Application Processor for Embedded Systems *Chun-Jen Tsai, Tsung-Han Wu, Hung-Cheng Su, Cheng-Yang Chen*	170-192
Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach *Alessandro Danese, Francesca Filini, Tara Ghasempouri, Graziano Pravadelli*	193-221

Designed by Inria-IES Team : Hosted by HAL :