index - VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability

Table of Contents
VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability *Thomas Hollstein, Jaan Raik, Sergei Kostin, Anton Tšertov, Ian O'Connor, Ricardo Reis*	Front Matter
Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures *Xueqing Li, Kaisheng Ma, Sumitha George, John Sampson, Vijaykrishnan Narayanan*	1-23
Logic with Unipolar Memristors – Circuits and Design Methodology *Nimrod Wald, Elad Amrani, Avishay Drori, Shahar Kvatinsky*	24-40
Robust Hybrid TFET-MOSFET Circuits in Presence of Process Variations and Soft Errors *Maedeh Hemmat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram*	41-59
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits *Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino*	60-82
Digital Hardware Design Based on Metamodels and Model Transformations *Johannes Schreiner, Wolfgang Ecker*	83-107
Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings *Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Shaker Sarwary, Dominique Borrione*	108-129
Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs *Paolo Bernardi, Alberto Bosio, Giorgio Natale, Andrea Guerriero, Ernesto Sanchez, Federico Venini*	130-151
Beyond Ideal DVFS Through Ultra-Fine Grain Vdd-Hopping *Enrico Macii, Massimo Alioto, Valentino Peluso, Roberto Rizzo, Andrea Calimera*	152-172
Earth Mover’s Distance as a Comparison Metric for Analog Behavior *Alexander Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker*	173-191
Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO *Syed Abbas, Chi-Ying Tsui*	192-212
A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA *Yanzhe Li, Kai Huang, Luc Claesen*	213-232

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