Skip to Main content Skip to Navigation
Conference papers

Speeding Up Galois Field Arithmetic on Intel MIC Architecture

Abstract : Galois Field arithmetic is the basis of LRC, RS and many other erasure coding approaches. Traditional implementations of Galois Field arithmetic use multiplication tables or discrete logarithms, which limit the speed of its computation. The Intel Many Integrated Core (MIC) Architecture provides 60 cores on chip and very wide 512-bit SIMD instructions, attractive for data intensive applications. This paper demonstrates how to leverage SIMD instructions and shared memory multiprocessing on MIC to perform Galois Field arithmetic. The experiments show that the performance of the computation is significantly enhanced.
Document type :
Conference papers
Complete list of metadatas

Cited literature [14 references]  Display  Hide  Download

https://hal.inria.fr/hal-01513765
Contributor : Hal Ifip <>
Submitted on : Tuesday, April 25, 2017 - 2:33:31 PM
Last modification on : Tuesday, April 25, 2017 - 2:35:50 PM
Long-term archiving on: : Wednesday, July 26, 2017 - 2:05:09 PM

File

978-3-642-40820-5_13_Chapter.p...
Files produced by the author(s)

Licence


Distributed under a Creative Commons Attribution 4.0 International License

Identifiers

Citation

Kai Feng, Wentao Ma, Wei Huang, Qing Zhang, Yili Gong. Speeding Up Galois Field Arithmetic on Intel MIC Architecture. 10th International Conference on Network and Parallel Computing (NPC), Sep 2013, Guiyang, China. pp.143-154, ⟨10.1007/978-3-642-40820-5_13⟩. ⟨hal-01513765⟩

Share

Metrics

Record views

179

Files downloads

469