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Silicon Test Structures Design for Sub-THz and THz Measurements

Marco Cabbia 1 Chandan Yadav 1, 2 Marina Deng 1 Sebastien Fregonese 1 Magali de Matos 1 Thomas Zimmer 1
1 IMS - Laboratoire de l'intégration, du matériau au système
2 National Institute of Technology Calicut
Abstract : In this paper, we present on-wafer TRL-calibrated measurements of silicon test structures fabricated using STMi-croelectronics' B55 technology up to 500 GHz. The structures are fabricated in two subsequent runs and the respective structure in each run has a different design. The improvements in the test structures layout design are presented on the terminal capaci-tances of "open-M1", which is an important test structure for the de-embedding of the transistor accesses. The improvements are examined using HFSS electromagnetic (EM) simulations, including the RF probe models and the neighboring structures.
Keywords : Calibration Probes Layout Radio frequency Transistors Integrated circuit modeling Couplings Characterization electromagnetic (EM) simulation high-frequency structure simulator (HFSS) terahertz (THz) test structures thru-reflect-line (TRL) calibration.
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https://hal.archives-ouvertes.fr/hal-03015973
Contributor : Frédérique Flamerie de Lachapelle <>
Submitted on : Friday, November 20, 2020 - 10:35:32 AM
Last modification on : Friday, November 27, 2020 - 3:22:02 AM

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IMS-BORDEAUX-FUSION | IMS-BORDEAUX | CNRS

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Marco Cabbia, Chandan Yadav, Marina Deng, Sebastien Fregonese, Magali de Matos, et al.. Silicon Test Structures Design for Sub-THz and THz Measurements. IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2020, pp.1-7. ⟨10.1109/TED.2020.3031575⟩. ⟨hal-03015973⟩

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