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Communication dans un congrès

Analytical Cache Modeling and Tilesize Optimization for Tensor Contractions

Abstract : Data movement between processor and memory hierarchy is a fundamental bottleneck that limits the performance of many applications on modern computer architectures. Tiling and loop permutation are key techniques for improving data locality. However, selecting effective tile-sizes and loop permutations is particularly challenging for tensor contractions due to the large number of loops. Even state-of-the-art compilers usually produce sub-optimal tile-sizes and loop permutations, as they rely on naive cost models. In this paper we provide an analytical model based approach to multi-level tile size optimization and permutation selection for tensor contractions. Our experimental results show that this approach achieves comparable or better performance than state-of-theart frameworks and libraries for tensor contractions.
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https://hal.inria.fr/hal-02418875
Contributeur : Fabrice Rastello <>
Soumis le : jeudi 19 décembre 2019 - 10:53:57
Dernière modification le : jeudi 19 novembre 2020 - 13:02:12
Archivage à long terme le : : vendredi 20 mars 2020 - 14:10:45

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Rui Li, Aravind Sukumaran-Rajam, Richard Veras, Tze Meng Low, Fabrice Rastello, et al.. Analytical Cache Modeling and Tilesize Optimization for Tensor Contractions. SC 2019 - International Conference for High Performance Computing, Networking, Storage and Analysis, Nov 2019, Denver, United States. pp.1-13, ⟨10.1145/3295500.3356218⟩. ⟨hal-02418875⟩

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