WCET analysis of instruction cache hierarchies

Damien Hardy 1, * Isabelle Puaut 1
* Auteur correspondant
1 ALF - Amdahl's Law is Forever
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : With the advent of increasingly complex hardware in real-time embedded systems (processors with performance enhancing features such as pipelines, caches, multiple cores), most embedded processors use a hierarchy of caches. While much research has been devoted to the prediction of Worst-Case Execution Times (WCETs) in the presence of a single level of cache (instruction caches, data caches, impact of cache replacement policies), very little research has focused on WCET estimations in the presence of cache hierarchies. In this paper, we propose a safe static instruction cache analysis method for multi-level caches. Variations of the method are presented to model different cache hierarchy management policies between cache levels: non-inclusive, inclusive and exclusive cache hierarchies. The method supports multiple replacement policies. The proposed method is experimented on medium-size benchmarks and a larger application. We show that the method is tight in the case of non-inclusive caches hierarchies and exclusive caches hierarchies, provided that all cache levels use the Least Recently Used (LRU) replacement policy. We further evaluate the additional pessimism when inclusion is enforced or when a non-LRU replacement policy is used.
Type de document :
Article dans une revue
Journal of system architecture, Elsevier, 2011, 57 (7), 〈10.1016/j.sysarc.2010.08.007〉
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https://hal.inria.fr/hal-00639454
Contributeur : Isabelle Puaut <>
Soumis le : mercredi 9 novembre 2011 - 11:37:43
Dernière modification le : mardi 16 janvier 2018 - 15:54:17

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Damien Hardy, Isabelle Puaut. WCET analysis of instruction cache hierarchies. Journal of system architecture, Elsevier, 2011, 57 (7), 〈10.1016/j.sysarc.2010.08.007〉. 〈hal-00639454〉

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