Hardware acceleration of sequential loops

Pierre Michaud 1
1 ALF - Amdahl's Law is Forever
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : The current trend in general-purpose microprocessors is to take advantage of Moore's law to increase the number of cores on the same chip. In a few technology generations, this will lead to chips with hundreds of superscalar cores. Obtaining high performance on these so-called many-cores will require to parallelize the applications. Nevertheless, it is unlikely that all the applications will take full advantage of the high number of cores. Hence it is important, along with increasing the number of cores, to increase sequential performance and dedicate a relatively large silicon area and power budget for that purpose. In this study, we consider the possibility to increase sequential performance with a loop accelerator. The loop accelerator sits beside a conventional superscalar core and is specialized for executing dynamic loops, i.e., periodic sequences of dynamic instructions. Loops are detected and accelerated automatically, without help from the programmer or the compiler. The execution is migrated from the superscalar core to the loop accelerator when a dynamic loop is detected, and back to the superscalar core when a loop exit condition is encountered. We describe the proposed loop accelerator and we study its performance on the SPEC CPU2006 applications. We show that significant performance gains may be achieved on some applications.
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Reports
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https://hal.inria.fr/hal-00641350
Contributor : Pierre Michaud <>
Submitted on : Tuesday, November 15, 2011 - 2:59:08 PM
Last modification on : Thursday, November 15, 2018 - 11:57:43 AM
Long-term archiving on : Thursday, February 16, 2012 - 2:27:44 AM

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  • HAL Id : hal-00641350, version 1

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Pierre Michaud. Hardware acceleration of sequential loops. [Research Report] RR-7802, INRIA. 2011. ⟨hal-00641350⟩

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