Parametric Multi-Level Tiling of Imperfectly Nested Loops

Abstract : Tiling is a crucial loop transformation for generating high perfor- mance code on modern architectures. Efficient generation of multi- level tiled code is essential for maximizing data reuse in systems with deep memory hierarchies. Tiled loops with parametric tile sizes (not compile-time constants) facilitate runtime feedback and dynamic optimizations used in iterative compilation and automatic tuning. Previous parametric multi-level tiling approaches have been restricted to perfectly nested loops, where all assignment state- ments are contained inside the innermost loop of a loop nest. Pre- vious solutions to tiling for imperfect loop nests have only handled fixed tile sizes. In this paper, we present an approach to paramet- ric multi-level tiling of imperfectly nested loops. The tiling tech- nique generates loops that iterate over full rectangular tiles, making them amenable to compiler optimizations such as register tiling. Experimental results using a number of computational benchmarks demonstrate the effectiveness of the developed tiling approach.
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Communication dans un congrès
23rd International Conference on Supercomputing, Jun 2009, Yorkton Heights, New York, United States. 2009
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Albert Hartono, Muthu Baskaran, Cédric Bastoul, Albert Cohen, Sriram Krishnamoorthy, et al.. Parametric Multi-Level Tiling of Imperfectly Nested Loops. 23rd International Conference on Supercomputing, Jun 2009, Yorkton Heights, New York, United States. 2009. 〈hal-00645328〉

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