Abstract : To keep up with a large degree of ILP, Itanium2 L2 cache system uses a complex organization scheme: load/store queues, banking and interleaving. In this paper, we study the impact of this cache system on memory instruction scheduling. We demonstrate that for scientific codes, "memory access vectorization" allows to generate very efficient code (up to the maximum of 4 loads per cycle). The impact of such "vectorization" on register pressure is analyzed: various register allocation schemes are proposed and evaluated.
Type de document :
Communication dans un congrès
Workshop on Compilers for Parallel Computers, Jan 2003, Amsterdam, Netherlands. 2003
https://hal.inria.fr/hal-00647124
Contributeur : Sid Touati
<>
Soumis le : jeudi 1 décembre 2011 - 15:14:44
Dernière modification le : jeudi 11 janvier 2018 - 06:21:30
Document(s) archivé(s) le : vendredi 2 mars 2012 - 02:30:28
William Jalby, Christophe Lemuet, Sid Touati. Efficient Code Optimization Technique for Itanium2 Cache System and Scientific Computing. Workshop on Compilers for Parallel Computers, Jan 2003, Amsterdam, Netherlands. 2003. 〈hal-00647124〉
