To keep up with a large degree of ILP, Itanium2 L2 cache system uses a complex organization scheme: load/store queues, banking and interleaving. In this paper, we study the impact of this cache system on memory instruction scheduling. We demonstrate that for scientific codes, "memory access vectorization" allows to generate very efficient code (up to the maximum of 4 loads per cycle). The impact of such "vectorization" on register pressure is analyzed: various register allocation schemes are proposed and evaluated.