H. Vicki, R. B. Allan, R. M. Jones, S. J. Lee, and . Allan, Software pipelining, ACM Computing Surveys, vol.27, issue.3, pp.367-432, 1995.

E. Altman, Optimal Software Pipelining with Functional Units and Registers, 1995.

E. Eda96-]-alexandre, E. S. Eichenberger, S. G. Davidson, and . Abraham, Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling, International Journal of Parallel Programming, vol.24, issue.2, pp.103-132, 1996.

[. Eisenbeis, F. Gasperoni, and U. Schwiegelshohn, Allocating Registers in Multiple Instruction-Issuing Processors, Proceedings of the IFIP WG
URL : https://hal.archives-ouvertes.fr/inria-00074059

[. Eisenbeis, S. Lelait, and B. Marmol, The meeting graph: A new model for loop cyclic register allocation, Proceedings of the IFIP WG 10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '95, pp.264-267, 1995.

C. Eisenbeis and A. Sawaya, Optimal Loop Parallelization under Register Constraints, Sixth Workshop on Compilers for Parallel Computers CPC'96, pp.245-259, 1996.
URL : https://hal.archives-ouvertes.fr/inria-00073911

C. Eisenbeis and A. Sawaya, Optimal Loop Parallelization under Register Constraints, 1996.
URL : https://hal.archives-ouvertes.fr/inria-00073911

E. [. Govindarajan, G. R. Altman, and . Gao, Minimizing register requirements under resource-constrained rate-optimal software pipelining, Proceedings of the 27th annual international symposium on Microarchitecture , MICRO 27, pp.85-94, 1994.
DOI : 10.1145/192724.192733

]. R. Huf93 and . Huff, Lifetime-Sensitive Modulo Scheduling, PLDI 93, pp.258-267, 1993.

A. [. Llosa, E. Gonzalez, M. Ayguadé, and . Valero, Swing Modulo Scheduling: A Lifetime-Sensitive Approach, PACT 96, 1996.

J. Llosa, Reducing the Impact of Register Pressure on Software Pipelined Loops, 1996.

M. [. Llosa, E. Valero, and . Ayguadé, Hypernode Reduction Modulo Scheduling, pp.350-360, 1995.
DOI : 10.1109/micro.1995.476844

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

M. Waleed, E. S. Meleis, and . Davidson, Dual-Issue Scheduling with Spills for Binary Trees, Proceedings of the Tenth Annual ACM-SIAM Symposium on Discrete Algorithms, pp.678-686, 1999.

]. I. Nak67 and . Nakata, On Compiling Algorithms for Arithmetic Expressions, Communications of the ACM, vol.10, pp.492-494, 1967.

Q. Ning and G. R. Gao, A novel framework of register allocation for software pipelining, Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages , POPL '93, pp.29-42, 1993.
DOI : 10.1145/158511.158519

[. Ning, Optimal Register Allocation to Support Time Optimal Scheduling for Loops, 1993.

]. R. Red69 and . Redziejowski, On Arithmetic Expressions and Trees, Communications of the ACM, vol.12, issue.2, pp.81-84, 1969.

M. [. Rau, P. P. Lee, M. S. Tirumalai, and . Schlansker, Register allocation for software pipelined loops, Proceedings of the ACM SIGPLAN '92 Conference on Programming Language Design and Implemen- tation, pp.283-299, 1992.
DOI : 10.1145/143103.143141

F. Sanchez and J. Cortadella, RE- SIS: A New Methodology for Register Optimization in Software Pipelining, Proceedings of Second International Euro-Par Conference, Euro-Par'96, 1996.

[. Strout, L. Carter, J. Ferrante, B. Simon, R. Sethisu70-]-r et al., Scheduleindependent storage mapping for loops Complete register allocation problems The Generation of Optimal Code for Arithmetic Expressions, Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems, pp.24-33226, 1970.

[. Touati, Optimal Register Saturation in Acyclic Superscalar and VLIW Codes ftp.inria.fr/INRIA/Projects/a3/touati/optiRS.ps.gz. [Tou01a] Sid-Ahmed-Ali Touati. EquiMax: A New Formulation of Acyclic Scheduling Problem for ILP Processors, Interaction between Compilers and Computer Architectures, 2000.

[. Touati, Maximizing for Reducing Register Need in Acyclic Schedules, Proceedings of 5th International Workshop on Software and Compilers for Embedded Systems, 2001.
URL : https://hal.archives-ouvertes.fr/hal-00646770

[. Touati, Optimal Acyclic Fine-Grain Schedule with Cache Effects for Embedded and Real Time Systems, Proceedings of 9th nternational Symposium on Hardware/Software Codesign, CODES, 2001.

[. Touati, Register Saturation in Superscalar and VLIW Codes, Proceedings of The International Conference on Compiler Construction, 2001.
DOI : 10.1007/3-540-45306-7_15

URL : https://hal.archives-ouvertes.fr/inria-00637277

[. Wang, C. Eisenbeis, M. Jourdan, and B. Su, Decomposed software pipelining: A new perspective and a new approach, International Journal of Parallel Programming, vol.19, issue.7, pp.351-373, 1994.
DOI : 10.1007/BF02577737

[. Wang, A. Krall, and M. A. Ertl, Decomposed Software Pipelining with Reduced Register Requirement, Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT95, pp.277-280, 1995.

[. Wang, A. Krall, M. A. Ertl, and C. Eisenbeis, Software pipelining with register allocation and spilling, Proceedings of the 27th annual international symposium on Microarchitecture , MICRO 27, pp.95-99, 1994.
DOI : 10.1145/192724.192734