Performance modeling for power consumption reduction on SCC

Bertrand Putigny 1, 2 Brice Goglin 2, 1 Denis Barthou 2, 1
1 RUNTIME - Efficient runtime systems for parallel architectures
Inria Bordeaux - Sud-Ouest, UB - Université de Bordeaux, CNRS - Centre National de la Recherche Scientifique : UMR5800
2 LaBRI - Laboratoire Bordelais de Recherche en Informatique
Abstract : As power is becoming one of the biggest challenge in high performance computing, we are proposing a performance model on the Single-chip Cloud Computer in order to predict both power consumption and runtime of regular codes. This model takes into account the frequency at which the cores of the SCC chip operate. Thus, we can predict the execution time and power needed to run the code for each available frequency. This allows to choose the best frequency to optimize several metrics such as power efficiency or minimizing power consumption, based on the needs of the application. Our model only needs some parameters that are code dependent. These parameters can be found through static code analysis. We validated our model by showing that it can predict performance and find the optimal frequency divisor to optimize energy efficiency on several dense linear algebra codes.
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Communication dans un congrès
Hasso Plattner Institute at University of Potsdam. 4th Many-core Applications Research Community (MARC) Symposium, Dec 2011, Potsdam, Germany. 2011
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Contributeur : Bertrand Putigny <>
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Dernière modification le : jeudi 11 janvier 2018 - 06:22:12
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Bertrand Putigny, Brice Goglin, Denis Barthou. Performance modeling for power consumption reduction on SCC. Hasso Plattner Institute at University of Potsdam. 4th Many-core Applications Research Community (MARC) Symposium, Dec 2011, Potsdam, Germany. 2011. 〈hal-00649635〉

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