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Performance modeling for power consumption reduction on SCC
Abstract : As power is becoming one of the biggest challenge in high performance computing, we are proposing a performance model on the Single-chip Cloud Computer in order to predict both power consumption and runtime of regular codes. This model takes into account the frequency at which the cores of the SCC chip operate. Thus, we can predict the execution time and power needed to run the code for each available frequency. This allows to choose the best frequency to optimize several metrics such as power efficiency or minimizing power consumption, based on the needs of the application. Our model only needs some parameters that are code dependent. These parameters can be found through static code analysis. We validated our model by showing that it can predict performance and find the optimal frequency divisor to optimize energy efficiency on several dense linear algebra codes.
Cited literature [12 references]
https://hal.inria.fr/hal-00649635
Contributor : Bertrand Putigny <>
Submitted on : Friday, March 1, 2013 - 9:44:48 AM
Last modification on : Wednesday, May 15, 2019 - 5:24:09 PM
Document(s) archivé(s) le : Sunday, June 2, 2013 - 2:20:11 AM
Contributor : Bertrand Putigny <>
Submitted on : Friday, March 1, 2013 - 9:44:48 AM
Last modification on : Wednesday, May 15, 2019 - 5:24:09 PM
Document(s) archivé(s) le : Sunday, June 2, 2013 - 2:20:11 AM
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