A design methodology for specification and performances evaluation of Network On Chip

Djamel Adrouche 1 Rabah Sadoun 1 Sébastien Pillement 2
1 ENP - Ecole Nationale Polytechnique [Alger]
2 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Document type :
Conference papers
Complete list of metadatas
https://hal.inria.fr/hal-00650595
Contributor : Sébastien Pillement <>
Submitted on : Sunday, December 11, 2011 - 11:41:05 AM
Last modification on : Wednesday, December 18, 2019 - 4:59:29 PM

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  • HAL Id : hal-00650595, version 1

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Djamel Adrouche, Rabah Sadoun, Sébastien Pillement. A design methodology for specification and performances evaluation of Network On Chip. IEEE International Workshop on Reliability Aware System Design and Test, 2011, Chennai, India. ⟨hal-00650595⟩

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