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A design methodology for specification and performances evaluation of Network On Chip

Djamel Adrouche 1 Rabah Sadoun 1 Sébastien Pillement 2
1 ENP - Ecole Nationale Polytechnique [Alger]
2 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
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Conference papers
Complete list of metadatas
https://hal.inria.fr/hal-00650595
Contributor : Sébastien Pillement <>
Submitted on : Sunday, December 11, 2011 - 11:41:05 AM
Last modification on : Friday, July 10, 2020 - 4:08:49 PM

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  • HAL Id : hal-00650595, version 1

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CNRS | INRIA | UNIV-RENNES1 | IRISA | IRISA-D3 | INSTITUT-TELECOM | UR1-UFR-ISTIC | UNIV-RENNES | INSA-RENNES

Citation

Djamel Adrouche, Rabah Sadoun, Sébastien Pillement. A design methodology for specification and performances evaluation of Network On Chip. IEEE International Workshop on Reliability Aware System Design and Test, 2011, Chennai, India. ⟨hal-00650595⟩

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