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FPGA modeling for SoC design exploration

Dominique Blouin 1 Eric Senn 2 Robin Bonamy 3 Daniel Chillet 3 Sebastien Bilavarn 4 Christian Samoyeau 5
1 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)
2 Lab-STICC_UBS_CACS_MOCS
Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
3 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
4 LEAT - Laboratoire d'Electronique, Antennes et Télécommunications
5 InPixal [Rennes]
Document type :
Conference papers
Complete list of metadatas
https://hal.inria.fr/hal-00650630
Contributor : Daniel Chillet <>
Submitted on : Sunday, December 11, 2011 - 9:14:29 PM
Last modification on : Friday, July 10, 2020 - 4:01:34 PM

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  • HAL Id : hal-00650630, version 1

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INSTITUT-TELECOM | CNRS | INRIA | UNIV-RENNES1 | IRISA | UNIV-BREST | UNICE | LAB-STICC | IRISA-D3 | UR1-UFR-ISTIC | ENIB | LAB-STICC_ENIB | UNIV-COTEDAZUR | UNIV-RENNES | LAB-STICC_UBS | UBS | INSA-RENNES

Citation

Dominique Blouin, Eric Senn, Robin Bonamy, Daniel Chillet, Sebastien Bilavarn, et al.. FPGA modeling for SoC design exploration. HEART (International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies, Imperial college, Jun 2011, London, United Kingdom. ⟨hal-00650630⟩

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