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FPGA modeling for SoC design exploration

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https://hal.inria.fr/hal-00650630
Contributor : Daniel Chillet <>
Submitted on : Sunday, December 11, 2011 - 9:14:29 PM
Last modification on : Friday, July 10, 2020 - 4:01:34 PM

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  • HAL Id : hal-00650630, version 1

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Dominique Blouin, Eric Senn, Robin Bonamy, Daniel Chillet, Sebastien Bilavarn, et al.. FPGA modeling for SoC design exploration. HEART (International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies, Imperial college, Jun 2011, London, United Kingdom. ⟨hal-00650630⟩

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