Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network

Daniel Chillet; Antoine Eiche; Sébastien Pillement; Olivier Sentieys

doi:10.1016/j.sysarc.2011.01.004

Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network

Daniel Chillet ¹ Antoine Eiche ¹ Sébastien Pillement ¹ Olivier Sentieys ¹

1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources

Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE

Keywords : Artificial neural network Heterogeneous multi-processor architecture Hopfield model Inhibitor neurons Task scheduling

Type de document :

Article dans une revue

Journal of System Architectures, Elsevier North-Holland, Inc., 2011, 57, pp.340-353. 〈10.1016/j.sysarc.2011.01.004〉

Liste complète des métadonnées

https://hal.inria.fr/hal-00650650
Contributeur : Daniel Chillet <>
Soumis le : dimanche 11 décembre 2011 - 22:06:07
Dernière modification le : mercredi 16 mai 2018 - 11:23:26

Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network

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Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network

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