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Journal articles

Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network

Daniel Chillet 1 Antoine Eiche 1 Sébastien Pillement 1 Olivier Sentieys 1 
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Keywords : Artificial neural network Heterogeneous multi-processor architecture Hopfield model Inhibitor neurons Task scheduling
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Journal articles
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https://hal.inria.fr/hal-00650650
Contributor : Daniel Chillet Connect in order to contact the contributor
Submitted on : Sunday, December 11, 2011 - 10:06:07 PM
Last modification on : Thursday, January 20, 2022 - 5:33:18 PM

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INSTITUT-TELECOM | EC-PARIS | UNIV-RENNES1 | CNRS | INRIA | INSA-RENNES | IRISA | IETR | IRISA-D3 | INRIA2 | UR1-MATH-STIC | UR1-UFR-ISTIC | UNIV-RENNES | UR1-MATH-NUM

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Daniel Chillet, Antoine Eiche, Sébastien Pillement, Olivier Sentieys. Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network. Journal of Systems Architecture, Elsevier, 2011, 57, pp.340-353. ⟨10.1016/j.sysarc.2011.01.004⟩. ⟨hal-00650650⟩

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