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Simultaneous floating-point sine and cosine for VLIW integer processors

Claude-Pierre Jeannerod 1, * Jingyan Jourdan-Lu 1, 2, *
* Corresponding author
1 ARIC - Arithmetic and Computing
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
2 Compilation Expertise Center
ST-GRENOBLE - STMicroelectronics [Grenoble]
Abstract : Graphics and signal processing applications often require that sines and cosines be evaluated at a same floating-point argument, and in such cases a very fast computation of the pair of values is desirable. This paper studies how 32-bit VLIW integer architectures can be exploited in order to perform this task accurately for IEEE single precision. We describe software implementations for sinf, cosf, and sincosf over [-pi/4,pi/4] that have a proven 1-ulp accuracy and whose latency on STMicroelectronics' ST231 VLIW integer processor is 19, 18, and 19 cycles, respectively. Such performances are obtained by introducing a novel algorithm for simultaneous sine and cosine that combines univariate and bivariate polynomial evaluation schemes.
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Contributor : Claude-Pierre Jeannerod <>
Submitted on : Tuesday, February 21, 2012 - 9:43:11 AM
Last modification on : Saturday, September 11, 2021 - 3:18:17 AM
Long-term archiving on: : Friday, November 23, 2012 - 2:10:46 PM


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  • HAL Id : hal-00672327, version 1



Claude-Pierre Jeannerod, Jingyan Jourdan-Lu. Simultaneous floating-point sine and cosine for VLIW integer processors. 23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2012), Jul 2012, Delft, Netherlands. pp.69-76. ⟨hal-00672327⟩



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