B. Bailey, System level virtual prototyping becomes a reality with OVP donation from imperas, 2008.

G. Beltrame, L. Fossati, and D. Sciuto, ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.28, issue.12, pp.1857-1869, 2009.

D. Brooks, V. Tiwari, and M. Martonosi, Wattch: A framework for architectural-level power analysis and optimizations, Proc. International Symposium on Computer Architecture ISCA'00, pp.83-94, 2000.

Y. Chen, The Analysis and Practice on Open Source Embedded System Software?Based on SkyEye and ARM Developing Platform, 2004.

N. Dhanwada, R. A. Bergamaschi, W. W. Dungan, I. Nair, P. Gramann et al., Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems, Design Automation for Embedded Systems, vol.10, issue.2-3
DOI : 10.1007/s10617-006-9586-7

S. Dhouib, J. Diguet, D. Blouin, and J. Laurent, Energy and Power Consumption Estimation for Embedded Applications and Operating Systems, Journal of Low Power Electronics, vol.5, issue.4, 2009.
DOI : 10.1166/jolpe.2009.1041
URL : https://hal.archives-ouvertes.fr/hal-00429454

J. Laurent, N. Julien, and E. Martin, High level energy estimation for DSP systems, Proc. Int. Workshop on Power And Timing Modeling, Optimization and Simulation PATMOS'01, pp.311-316, 2001.
URL : https://hal.archives-ouvertes.fr/hal-00077563

J. Laurent, N. Julien, and E. Martin, Functional level power analysis: an efficient approach for modeling the power consumption of complex processors, Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004.
DOI : 10.1109/DATE.2004.1268921
URL : https://hal.archives-ouvertes.fr/hal-00013979

J. Laurent, N. Julien, and E. Martin, Softexplorer: estimation, characterization and optimization of the power and energy consumption at the algorithmic level, Fourteenth International Workshop on Power and Timing Modeling, pp.15-17, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00013977

I. Lee, H. Kim, P. Yang, S. Yoo, E. Chung et al., P, Proceedings of the 2006 conference on Asia South Pacific design automation , ASP-DAC '06, 2006.
DOI : 10.1145/1118299.1118431
URL : https://hal.archives-ouvertes.fr/jpa-00224550

N. Dhanwada, I. Lin, and V. Narayanan, A power estimation methodology for systemC transaction level models, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '05, 2005.
DOI : 10.1145/1084834.1084874

J. D. Douhib, Model driven high-level power estimation of embedded operating systems communication and synchronization services, Proceedings of the 6th IEEE International Conference on Embedded Software and Systems, China, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00489833

V. Tiwari, S. Malik, and A. Wolfe, Power analysis of embedded software: A first step towards software power minimization, Transactions on VLSI Systems, 1994.

W. Ye, N. Vijaykrishnam, M. Kandemir, and M. Irwin, The design and use of simplepower, Proceedings of the 37th conference on Design automation , DAC '00, 2000.
DOI : 10.1145/337292.337436