J. D. Allen and D. E. Schimmel, Issues in the design of high performance SIMD architectures, IEEE Transactions on Parallel and Distributed Systems, vol.7, issue.8, pp.818-829, 1996.
DOI : 10.1109/71.532113

P. Marquet, S. Duquennoy, S. Lebeux, S. Meftaly, and J. Dekeyser, Massively parallel processing on a chip, Proceedings of the 4th international conference on Computing frontiers , CF '07, pp.277-286, 2007.
DOI : 10.1145/1242531.1242571

URL : https://hal.archives-ouvertes.fr/hal-00688418

A. Kamis and H. Topi, Network Subnetting: An Instance of Technical Problem Solving in Kolb's Experiential Learning Cycle, 2007 40th Annual Hawaii International Conference on System Sciences (HICSS'07), 2007.
DOI : 10.1109/HICSS.2007.399

K. Chung, ILP-SIMD : an instruction parallel SIMD architecture with short-wire interconnects, PhD, Georgia Institute of Technology, 2000.

M. Bolotski, R. Amirtharajah, W. Chen, T. Kutscha, T. Simon et al., Abacus:a high-performance architecture for vision, Proc. of International Conference on Pattern Recognition, 1994.

E. Zehendner, Simulating systolic arrays on MasPar machines, EUROMICRO 97. Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology (Cat. No.97TB100167), pp.394-401, 1997.
DOI : 10.1109/EURMIC.1997.617337

J. Potter, J. Baker, S. Scott, A. Bansal, C. Leangsuksun et al., ASC: an associative-computing paradigm, Computer, vol.27, issue.11, pp.19-25, 1994.
DOI : 10.1109/2.330039

K. E. Batcher, STARAN parallel processor system hardware, Proceedings of the May 6-10, 1974, national computer conference and exposition on, AFIPS '74, 1974.
DOI : 10.1145/1500175.1500260

B. Parhami, Introduction to parallel processing: algorithms and architectures, 2002.

K. Schaffer and R. A. Walker, SMTASC: A Multithreaded Associative SIMD Processor, IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), pp.1776-1780, 2011.
DOI : 10.1109/ipdps.2011.335

S. Che, J. Li, J. W. Sheaffer, K. Skadron, and J. Lach, Accelerating Compute-Intensive Applications with GPUs and FPGAs, 2008 Symposium on Application Specific Processors, pp.101-107, 2008.
DOI : 10.1109/SASP.2008.4570793

M. Baklouti, M. Abid, P. Marquet, and J. Dekeyser, IP Based Configurable SIMD Massively Parallel SoC, 2010 International Conference on Field Programmable Logic and Applications, pp.247-250, 2010.
DOI : 10.1109/FPL.2010.57

URL : https://hal.archives-ouvertes.fr/inria-00525333

M. Baklouti, Y. Aydi, P. Marquet, M. Abid, and J. Dekeyse, Scalable mpNoC for massively parallel systems ??? Design and implementation on FPGA, Journal of Systems Architecture, vol.56, issue.7, pp.278-292, 2010.
DOI : 10.1016/j.sysarc.2010.04.001

URL : https://hal.archives-ouvertes.fr/inria-00525343

M. Baklouti, Méthode de conception rapide d'architecture massivement parallle sur puce: de la modlisation l'exprimentation sur FPGA, 2010.

T. Blank, The MasPar MP-1 architecture, Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage, pp.20-24, 1990.
DOI : 10.1109/CMPCON.1990.63648

M. Baklouti, M. Abid, P. Marquet, and J. Dekeyser, Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA, 2009 IEEE/ACS International Conference on Computer Systems and Applications, pp.368-373, 2009.
DOI : 10.1109/AICCSA.2009.5069350

R. Haskell and D. M. Hanna, A VHDL--Forth Core for FPGAs, Microprocessors and Microsystems, vol.28, issue.3, pp.115-125, 2004.
DOI : 10.1016/j.micpro.2004.01.002

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=