Software pipelining, ACM SIGPLAN Notices, vol.39, issue.4, pp.318-328, 1988. ,
DOI : 10.1145/989393.989420
Early Periodic Register Allocation on ILP Processors, Parallel Processing Letters, vol.14, issue.02, pp.287-313, 2004. ,
DOI : 10.1142/S012962640400188X
URL : https://hal.archives-ouvertes.fr/hal-00130623
ContributionàContribution`Contributionà l'allocation de registres dans les boucles, 1996. ,
Post-pass periodic register allocation to minimise loop unrolling degree, LCTES '08: Proceedings of the 2008 ACM SIGPLAN- SIGBED conference on Languages, compilers, and tools for embedded systems, pp.141-150, 2008. ,
URL : https://hal.archives-ouvertes.fr/inria-00637218
Code generation schema for modulo scheduled loops, Proceedings of the 25th Annual International Symposium on Microarchitecture, pp.158-169, 1992. ,
Embedded Computing: a VLIW Approach to Architecture, Compilers and Tools, 2005. ,
Lifetime-sensitive modulo scheduling, ACM SIGPLAN Notices, vol.28, issue.6, pp.258-267, 1993. ,
DOI : 10.1145/173262.155115
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.54.6852
Register Pressure in Instruction Level Parallelism, 2002. ,
DOI : 10.1007/s10766-005-6466-x
URL : https://hal.archives-ouvertes.fr/tel-00007405
Register allocation for software pipelined loops, ACM SIGPLAN Notices, vol.27, issue.7, pp.283-299, 1992. ,
DOI : 10.1145/143103.143141
On a graph-theoretical model for cyclic register allocation, Discrete Applied Mathematics, vol.93, issue.2-3 ,
DOI : 10.1016/S0166-218X(99)00105-5
A register allocation framework based on hierarchical cyclic interval graphs, CC '92: Proceedings of the 4th International Conference on Compiler Construction, pp.176-191, 1992. ,
DOI : 10.1007/3-540-55984-1_17
Lx, ACM SIGARCH Computer Architecture News, vol.28, issue.2, pp.203-213, 2000. ,
DOI : 10.1145/342001.339682