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Specification and Implementation of Digital Hopfield-Type Associative Memory with On-Chip Training

Abstract : This paper addresses the definition of the requirements for the design of a neural network associative memory, with on-chip training, in standard digital CMOS technology. We investigate various learning rules which are integrable in silicon, and we study the associative memory properties of the resulting networks. We also investigate the relationships between the architecture of the circuit and the learning rule, in order to minimize the extra circuitry required for the implementation of training. We describe a 64-neuron associative memory with on-chip training, which has been manufactured, and we outline its future extensions. Beyond the application to the specific circuit described in the paper, the general methodology for determining the accuracy requirements can be applied to other circuits and to other auto-associative memory architectures.
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https://hal.inria.fr/hal-00700043
Contributor : Jean-Dominique Gascuel <>
Submitted on : Tuesday, May 22, 2012 - 12:10:37 PM
Last modification on : Saturday, April 24, 2021 - 6:40:05 PM
Long-term archiving on: : Thursday, August 23, 2012 - 2:27:06 AM

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Anne Johannet, L. Personnaz, G. Dreyfus, Jean-Dominique Gascuel, M. Weinfeld. Specification and Implementation of Digital Hopfield-Type Associative Memory with On-Chip Training. IEEE Transactions on Neural Networks, Institute of Electrical and Electronics Engineers, 1992, 3 (4), pp.529-539. ⟨10.1109/72.143369⟩. ⟨hal-00700043⟩

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