A software reconfigurable multi-networks simulator using a custom associative chip

Abstract : A special-purpose simulator is described. It has been designed to try various interconnection schemes between several similar associative chips, in order to assess hierarchical assemblies of neural networks. These chips are digital feedback networks with 64 fully interconnected binary neurons, capable of on-chip learning and automatic detection of spurious attractors. This simulator is based on the MCP development board. Each such board can house four associative chips. The simulator is designed to transparently address chips not only inside the machine in which it resides, but also chips in other machines. All the virtual interconnections between chips are made at the neuron level, which means that the individual components of binary vectors processed by each chip can be routed to the input or from the output of any other chip. Simulator scheduling allows sequentiality in information processing
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Communication dans un congrès
Neural Networks, 1992. IJCNN., International Joint Conference on, Jun 1992, Baltimore, United States. 2, pp.13 -18, 1992, 〈http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=226991〉. 〈10.1109/IJCNN.1992.226991〉
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https://hal.inria.fr/hal-00700096
Contributeur : Jean-Dominique Gascuel <>
Soumis le : mardi 22 mai 2012 - 12:27:10
Dernière modification le : jeudi 11 janvier 2018 - 06:19:44

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J.-D. Gascuel, E. Delaunay, L. Montoliu, B. Moobed, M. Weinfeld. A software reconfigurable multi-networks simulator using a custom associative chip. Neural Networks, 1992. IJCNN., International Joint Conference on, Jun 1992, Baltimore, United States. 2, pp.13 -18, 1992, 〈http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=226991〉. 〈10.1109/IJCNN.1992.226991〉. 〈hal-00700096〉

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