Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

Abstract : One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for embedded systems are known to read and write data following memory access patterns. Memory access patterns can be used to optimize cache consistency by prefetching data and reducing the number of memory transactions. In this paper, we present the round-robin method applied to baseline coherency protocol and initial analysis of one hybrid protocol that performs speculative requests when access patterns are detected. We also propose to manage patterns through a dedicated hardware component attached to each core of the processor.
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Communication dans un congrès
IP-Embedded System Conference and Exhibition, Dec 2011, Grenoble, France. Design and Reuse, 20, 2011
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https://hal.inria.fr/hal-00712127
Contributeur : Loïc Cudennec <>
Soumis le : mardi 26 juin 2012 - 14:58:29
Dernière modification le : samedi 6 février 2016 - 01:09:18
Document(s) archivé(s) le : jeudi 27 septembre 2012 - 02:41:36

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Jussara Marandola, Loïc Cudennec. Co-Designed Cache Coherency Architecture for Embedded Multicore Systems. IP-Embedded System Conference and Exhibition, Dec 2011, Grenoble, France. Design and Reuse, 20, 2011. <hal-00712127>

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