M. Bachir, Loop Unrolling Minimisation for Periodic Register Allocation, 2010.

M. Bachir, D. Gregg, and S. Touati, Using the Meeting Graph Framework to Minimise Kernel Loop Unrolling for Scheduled Loops, Proceedings of the 22nd International Workshop on Languages and Compilers for Parallel Computing, 2009.
DOI : 10.1007/978-3-642-13374-9_19

URL : https://hal.archives-ouvertes.fr/hal-00643759

M. Bachir, S. Touati, and A. Cohen, Post-pass periodic register allocation to minimise loop unrolling degree, LCTES '08: Proceedings of the 2008 ACM SIGPLAN-SIGBED conference on Languages, compilers, and tools for embedded systems, pp.141-150, 2008.
URL : https://hal.archives-ouvertes.fr/inria-00637218

P. Briggs, K. D. Cooper, K. Kennedy, and L. Torczon, Coloring heuristics for register allocation, PLDI '89: Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation, pp.275-284, 1989.

G. Chaitin, Register allocation and spilling via graph coloring, ACM SIGPLAN Notices, vol.39, issue.4, pp.66-74, 2004.
DOI : 10.1145/989393.989403

D. De-werra, C. Eisenbeis, S. Lelait, and E. Stohr, Circular-arc graph coloring: On chords and circuits in the meeting graph, European Journal of Operational Research, vol.136, issue.3, pp.483-500, 2002.
DOI : 10.1016/S0377-2217(01)00058-3

J. C. Dehnert, Y. Peter, J. P. Hsu, and . Bratt, Overlapped loop support in the cydra 5, ASPLOS-III: Proceedings of the third international conference on Architectural support for programming languages and operating systems, pp.26-38, 1989.

M. R. Garey, D. S. Johnson, G. L. Miller, and C. H. Papadimitriou, The Complexity of Coloring Circular Arcs and Chords, SIAM Journal on Algebraic Discrete Methods, vol.1, issue.2, pp.216-227, 1980.
DOI : 10.1137/0601025

L. J. Hendren, G. R. Gao, E. R. Altman, and C. Mukerji, A register allocation framework based on hierarchical cyclic interval graphs, CC '92: Proceedings of the 4th International Conference on Compiler Construction, pp.176-191, 1992.
DOI : 10.1007/3-540-55984-1_17

R. A. Huff, Lifetime-sensitive modulo scheduling, ACM SIGPLAN Notices, vol.28, issue.6, pp.258-267, 1993.
DOI : 10.1145/173262.155115

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

P. Faraboschi, J. A. Fisher, and C. Young, Embedded Computing: a VLIW Approach to Architecture, Compilers and Tools, 2005.

M. Lam, Software pipelining, ACM SIGPLAN Notices, vol.39, issue.4, pp.318-328, 1988.
DOI : 10.1145/989393.989420

S. Lelait, G. R. Gao, and C. Eisenbeis, A new fast algorithm for optimal register allocation in modulo scheduled loops, Proceedings of the 7th International Conference on Compiler Construction, pp.204-218, 1998.
DOI : 10.1007/BFb0026433

URL : https://hal.archives-ouvertes.fr/inria-00073352

J. Llosa and S. M. Freudenberger, Reduced code size modulo scheduling in the absence of hardware support, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings., pp.99-110, 2002.
DOI : 10.1109/MICRO.2002.1176242

A. Nicolau, R. Potasman, and H. Wang, Register allocation, renaming and their impact on fine-grain parallelism, Proceedings of the Fourth International Workshop on Languages and Compilers for Parallel Computing, pp.218-235, 1992.
DOI : 10.1007/BFb0038667

B. R. Rau, M. Lee, P. P. Tirumalai, and M. S. Schlansker, Register allocation for software pipelined loops, ACM SIGPLAN Notices, vol.27, issue.7, pp.283-299, 1992.
DOI : 10.1145/143103.143141

S. Touati and C. Eisenbeis, Early Periodic Register Allocation on ILP Processors, Parallel Processing Letters, vol.14, issue.02, pp.287-313, 2004.
DOI : 10.1142/S012962640400188X

URL : https://hal.archives-ouvertes.fr/hal-00130623