Reducing thread divergence in a GPU-accelerated branch-and-bound algorithm

Abstract : In this paper, we address the design and implementation of GPU-accelerated Branch-and-Bound algorithms (B&B) for solving Flow-shop scheduling optimization problems (FSP). Such applications are CPU-time consuming and highly irregular. On the other hand, GPUs are massively multi-threaded accelerators using the SIMD model at execution. A major issue which arises when executing on GPU a B&B applied to FSP is thread or branch divergence. Such divergence is caused by the lower bound function of FSP which contains many irregular loops and conditional instructions. Our challenge is therefore to revisit the design and implementation of B&B applied to FSP dealing with thread divergence. Extensive experiments of the proposed approach have been carried out on well-known FSP benchmarks using an Nvidia Tesla C2050 GPU card. Compared to a CPU-based execution, accelerations up to ×77.46 are achieved for large problem instances.
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https://hal.inria.fr/hal-00731859
Contributor : Imen Chakroun <>
Submitted on : Thursday, September 13, 2012 - 4:22:47 PM
Last modification on : Thursday, April 4, 2019 - 10:18:06 AM
Long-term archiving on : Friday, December 14, 2012 - 3:58:06 AM

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Imen Chakroun, Mohand Mezmaz, Nouredine Melab, Ahcène Bendjoudi. Reducing thread divergence in a GPU-accelerated branch-and-bound algorithm. Concurrency and Computation: Practice and Experience, Wiley, 2012. ⟨hal-00731859⟩

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