Spatio-Temporal Scheduling for 3D Reconfigurable and Multiprocessor Architecture

Abstract : One of important benefits offered by three-dimensional integrated circuits (3D ICs) is the adap- tation to the heterogeneous systems where different types of components can be fabricated sepa- rately and layers can be implemented with different technologies. But stacking high performance technology for each layer is not sufficient to ensure that applications can exploit the overall per- formances. Indeed, one important challenge consists in defining a high performance management of such platform to guarantee that every execution resource is used as best as possible. This article addresses this challenge and proposes a spatio-temporal scheduling algorithm able to manage the instantiation of tasks on both homogeneous multiprocessor and reconfigurable layers. Our target architecture, based on 3D ICs technology, is then built by stacking an homogenous Chip MultiPro- cessor (CMP) layer above an homogeneous embedded Field-Programmable Gate Array (eFPGA) over through-silicon vias (TSVs) connection. Our algorithm computes the spatio-temporal sche- duling of hardware tasks on the reconfigurable resources by taking into account the communica- tion between tasks and then projects the associated software tasks on the multiprocessors layer. The communications are ensured by shared memory on the CMP layer, and by direct exchanges or shared memory on reconfigurable layer. The spatio-temporal scheduling is defined through an adaptation of the Proportionate-fair (Pfair) algorithm, which is well known to optimally schedule periodic real-time tasks on multiprocessor systems. Compare to the recursive Branch and Bound (BB) algorithm, our proposed algorithm shows up to 14,5% communication cost reduction.
Type de document :
Communication dans un congrès
Manifestation des Jeunes Chercheurs en Sciences et Technologies de l'Information et de la Communication, Oct 2012, Lille, France. 2012
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https://hal.inria.fr/hal-00741612
Contributeur : Daniel Chillet <>
Soumis le : dimanche 14 octobre 2012 - 21:13:14
Dernière modification le : jeudi 15 novembre 2018 - 11:57:39

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  • HAL Id : hal-00741612, version 1

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Quang Hai Khuat, Quang Hoa Le, Daniel Chillet, Sébastien Pillement. Spatio-Temporal Scheduling for 3D Reconfigurable and Multiprocessor Architecture. Manifestation des Jeunes Chercheurs en Sciences et Technologies de l'Information et de la Communication, Oct 2012, Lille, France. 2012. 〈hal-00741612〉

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