In multimedia applications, video and image processing is one of the challenges embedded systems have to face. Such applications are typically computationally intensive with control statements and designers have to cope with power and performance stringent requirements. The ROMA project proposes to develop both a design methodology and a reconfigurable processor able to adapt its computing structure to video and image processing applications. The reconfigurable processor is in charge of implementing parts of the code corresponding to loops and frequently executed computation code fragments that can be accelerated and/or which are good candidates to save power. It is built around a pipeline of coarse grain reconfigurable operators exhibiting interesting performance/power trade-off. The operators are designed such that their granularity matches the domain-specific computation patterns. Flexibility is obtained through these operators which can be configured for the function they implement and the width of the data. We have also developed a design flow to configure the processor. From the application source code, the software framework identifies the different computation patterns as well as their successive arrangements and completes transformations for the processor mapping.